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Buy P5010NSE7QMB with confidence from wisdommobility.com, 1 Year Warranty
See Product Specifications for product details.
Buy P5010NSE7QMB with confidence from wisdommobility.com, 1 Year Warranty
P5010NSE7QMB
| Part No | P5010NSE7QMB |
|---|---|
| Manufacturer | Freescale Semiconductor, Inc. (NXP Semiconductors) |
| Description | QorIQ, 64-Bit Power Arch SoC, 1.6GHz, DDR3, PCIe, GbE, SRIO, HW Accel, SEC, 0 to 105C Rev 2.0 |
| Lead Free Status / RoHS Status | Lead Free / RoHS compliant |
Specifications
Data sheet
| Core Processor | PowerPC e5500 |
|---|---|
| Clock Frequency | 166MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Integrated Cache | YES |
| Surface Mount | YES |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Height Seated (Max) | 3.53mm |
| Format | FIXED POINT |
| Terminal Position | BOTTOM |
| Package / Case | 1295-BBGA, FCBGA |
| Technology | CMOS |
| Address Bus Width | 16 |
| JESD-30 Code | S-PBGA-B1295 |
| Additional Interfaces | DUART, I2C, MMC/SD, SPI |
| Number of Cores/Bus Width | 1 Core 64-Bit |
| Terminal Form | BALL |
| Supply Voltage-Max (Vsup) | 1.15V |
| Supply Voltage | 1.1V |
| ECCN Code | 5A002.A.1 |
| Graphics Acceleration | No |
| SATA | SATA 3Gbps (2) |
| RoHS Status | ROHS3 Compliant |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Speed | 2.0GHz |
| Operating Temperature | 0°C~105°C TA |
| HTS Code | 8542.31.00.01 |
| Supply Voltage-Min (Vsup) | 1.05V |
| Security Features | Boot Security, Cryptography, Secure Fusebox, Secure JTAG, Secure Memory, Tamper Detection |
| USB | USB 2.0 + PHY (2) |
| Low Power Mode | YES |
| Boundary Scan | YES |
| External Data Bus Width | 64 |
| JESD-609 Code | e1 |
| Factory Lead Time | 26 Weeks |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Peak Reflow Temperature (Cel) | 245 |
| Series | QorIQ P5 |
| Length | 37.5mm |
| Ethernet | 1Gbps (5), 10Gbps (1) |
| Packaging | Tray |
| Part Status | Last Time Buy |
| RAM Controllers | DDR3, DDR3L |
| Published | 2002 |
| Terminal Pitch | 1mm |
| Co-Processors/DSP | Security; SEC 4.2 |
Introduce
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